1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor memory, and more particularly, it relates to a method of manufacturing a semiconductor memory of wiring width 0.8 .mu.m or under, with high yields.
2. Description of the Prior Art
A prior art embodiment and its disadvantages will be described with reference to diagrams for explaining structures of main parts of a semiconductor substrate.
In the prior art embodiment, as shown in FIGS. 5(a) and 5(b), after second underlayer wiring 73 is formed in a semiconductor substrate 71 which has first underlayer wiring (diffused layer) 72 formed by diffusing a layer insulating film 74 of SiO.sub.2 or the like is deposited; and thereafter, a contact hole 74a is formed by etching or the like. Upper wiring 75 is formed over the contact hole 74a; and thus, the wirings are electrically connected between the upper and lower layers.
In particular, in the case where the overlayer wiring 75 is made of a metal material like A1 while the first under layer wiring 72 is formed of the diffused layer formed in the substrate 71, it is likely that the metal wiring 75 and the substrate 71 are short-circuited in a part shown by an arrow Q in FIG. 6 when the contact hole 74a and the diffused layer, or the first underlayer wiring 72, are out of alignment. However, as shown in FIG. 7, such short-circuiting can be prevented if the surface of the substrate which is exposed because of the contact hole formed for the purpose of the connection with the first underlayer wiring 72 is covered with a polycrystalline Si film 76 doped with an impurity at high concentration so that the polycrystalline Si film 76 is interposed between the metal wiring 75 and the substrate 71. Specifically, the short-circuiting between the substrate 71 and the metal wiring 75 is prevented by covering the end of the diffused region exposed in the contact hole 74a with the polycrystalline Si film 76 which is doped with an impurity at high concentration. This is because an impurity with which the polycrystalline Si film 76 is doped at high concentration is diffused towards the substrate, so that no short-circuiting is caused even if the polycrystalline Si film 76 is deposited on the end of the diffused region.
Two problems arise in the above-mentioned way of covering the contact hole 74a with the polycrystalline Si film 76:
1) The distance between contact holes cannot be reduced.
For example, a case in which the polycrystalline Si film 76 covering the substrate 71 in the contact holes is etched will be discussed. When the polycrystalline Si film 76 is etched under the state where a part of the substrate is exposed because of the disregistration of the photoresist determining the configuration of the polycrystalline Si film 76 to be etched, the exposed portion is etched away as shown by an arrow R in FIG. 8 because the substrate is of silicon. The etching of the substrate may cause drawbacks such as a junction leak and the like. Hence, the end of the contact hole 74a in the polycrystalline Si film 76 must be positioned a distance d (0.1 .mu.m to 0.3 .mu.m) from the region where the substrate is exposed [see FIG. 11].
On the other hand, the lowermost limit of the distance between polycrystalline Si patterns is determined by the resolution of a light exposing projector. Thus, the minimum distance between the contact holes is about the double of the distance d (0.2 .mu.m to 0.6 .mu.m) added to the resolution (about 0.6 .mu.m) of the exposing projector. In other words, approximating a distance L between the contact holes 74a, 74a [see FIG. 11] to the resolution (about 0.6 .mu.m) of the exposing projector is impossible.
2) It is difficult to form the contact holes in self-alignment.
As shown in FIG. 9, the layer insulating film 74 is deposited on the second underlayer wiring 73, and then a portion where a contact hole is to be formed is etched down by the depth corresponding to the thickness of the layer insulating film 74 to form the contact hole on the surface of the substrate in self-alignment relative to the second underlayer wiring 73.
However, when a plurality of overlayer wiring layers 75 exist to connect with the substrate 71, layer insulating films 74, 77 and 78 and a polycrystalline Si film must be deposited on the substrate 71 at as many times. If the plurality of layers are deposited in such a manner, the layer insulating film on the underlayer wiring is larger in thickness than the layer insulating film on the contact hole enough to fill the contact hole with the insulating film, so that it is impossible to form the contact holes in self-alignment.
To overcome the above-mentioned problems, the present invention is directed to a method of manufacturing a semiconductor memory in which a contact hole assuredly making a contact with a diffused region of the semiconductor substrate can be formed while good yields of semiconductor memories can be attained even if the accuracy in the alignment of patterns in light projection and exposure is unsatisfactory.